The semiconductor industry has experienced exponential growth, and has progressed in pursuit of higher device density and performance, and lower costs. Technological advances in integrated circuit (IC) materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generations. In the course of IC evolution, functional density (for example, the number of interconnected devices per chip area) has generally increased while geometry sizes have decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
In the general manufacturing scheme of an IC, there are two major parts, the front end of line (FEOL) processing and the back end of line (BEOL) processing. In general, The BEOL contains passive, linear devices made from metals and insulators, such as signal and power wires, transmission lines, metal resistors, metal-insulator-metal (MIM) capacitors, inductors, fuses, etc., and the BEOL may include the devices being wired together with a patterned multilevel metallization process.
However, such scaling down has also increased the complexity of processing and manufacturing ICs. As higher device density and the scaling down, short circuits may frequently occur during the BEOL processing in ICs, resulting in the decrease of yield.
Accordingly, with the high demands on scaling down of the ICs, the method for forming such semiconductor structure has to be continuously improved so as to obtain a more satisfactory semiconductor structure.